Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, application specific integrated circuits (ASICs), and other specific functional circuits.
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, creating visual projections for television displays, and changing voltage levels. Semiconductor devices are found in the fields of entertainment, communications, power conversion, mechanical control, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
A charge pump circuit is an example of a specific functional circuit that can be implemented on a substrate in a semiconductor die. The charge pump circuit receives an input voltage and then provides a different output voltage, either higher or lower than the input voltage. A charge pump circuit may contain a number of cells cascaded together with a voltage level shift per cell. The overall level shift of the output voltage is determined by the number of cells in the charge pump circuit, each providing a voltage level shift. FIG. 1 illustrates a conventional dual bucket charge pump cell 10 including dual cross-coupled metal oxide semiconductor (MOS) inverters receiving capacitive-coupled complementary clock signals. The input terminal 12 of charge pump cell 10 receives voltage VLOW while terminal 14 provides cell output voltage VHIGH. Terminal 12 is coupled to a charge pump input voltage or terminal 14 of the preceding cell. Terminal 14 is coupled to terminal 12 of the next cell or provides the charge pump output voltage. Terminals 16 and 18 of charge pump cell 10 receive complementary clock signals CLK and nCLK of opposite phase. The clock signal CLK is coupled through capacitor 20 to the common gates of p-channel metal oxide semiconductor (PMOS) transistor 22 and n-channel metal oxide semiconductor (NMOS) transistor 24 at node 26. The clock signal nCLK is coupled through capacitor 28 to the common gates of PMOS transistor 30 and NMOS transistor 32 at node 34. The sources of transistors 22 and 30 are coupled to terminal 14. The drains of transistors 22 and 24 are coupled to node 34, and the drains of transistors 30 and 32 are coupled to node 26. The sources of transistors 24 and 32 are coupled to terminal 12 and VLOW.
For a p-type substrate, a “high or higher voltage” generally refers to a positive voltage less than or equal to the maximum positive operating potential and greater than a “low or lower voltage”, and the “low or lower voltage” generally refers to a positive voltage greater than or equal to the minimum operating potential (ground) and less than the “high or higher voltage.” An n-type substrate would have opposite voltages. A voltage VLOW, e.g., zero volts or other power supply potential, is applied to terminal 12. In cascaded charge pump cells, VHIGH from a previous cell is applied to terminal 12 as VLOW. Assume CLK is a high voltage, say +3 to +5 VDC, and nCLK is a low voltage, e.g., zero volts. When charge pump cell 10 is starting up, VLOW may be higher than VHIGH, which in turn is higher than or equal to Vsubstrate. The high CLK switches NMOS transistor 24 to a conductive state (VGS24 greater than threshold VTH of the transistor) and renders PMOS transistor 22 non-conductive (VGS22 not less than VTH). Capacitor 20 stores charge from the high CLK to increase the voltage at node 26. The low nCLK switches PMOS transistor 30 to a conductive state (VGS30 less than VTH) and renders NMOS transistor 32 non-conductive (VGS32 not greater than VTH). The conductive state of transistor 30 transfers the higher voltage at node 26 directly through the source-drain conduction path of transistor 30 to terminal 14 and causes VHIGH to increase toward the level of the clock signal, e.g., abs(CLK−nCLK)=3 VDC. The conductive state of transistor 24 discharges node 34 and capacitor 28 toward voltage VLOW.
In the opposite phase of the clock signal, a high nCLK renders PMOS transistor 30 non-conductive (VGS30 not less than VTH) and switches NMOS transistor 32 to a conductive state (VGS32 greater than threshold VTH). Capacitor 28 stores charge from the high nCLK to increase the voltage at node 34. The low CLK switches PMOS transistor 22 to a conductive state (VGS22 less than VTH) and renders NMOS transistor 24 non-conductive (VGS24 not greater than VTH). The conductive state of transistor 22 transfers the higher voltage at node 34 directly through the source-drain conduction path of transistor 22 to terminal 14 and causes VHIGH to increase toward the level of the clock signal, e.g., +3 VDC. The conductive state of transistor 32 discharges node 26 and capacitor 20 toward voltage VLOW. The process repeats each clock cycle as the cross-coupled inverter pairs 22-24 and 30-32 alternatingly charge and discharge capacitors 20 and 28 to transfer the voltage level of the clock signal either from node 26 or from node 34 to terminal 14. The discharge of capacitors 20 and 28 through transistors 24 and 32 resets nodes 26 and 34, respectively, each clock cycle to accurately track the voltage level of the clock signal.
In steady state, VHIGH has a value of the clock signal, e.g., abs(CLK−nCLK)=3 VDC. Accordingly, charge pump cell 10 has increased the voltage from VLOW=0 VDC to VHIGH=+3 VDC. Note that charge pump cell 10 is floating so for even higher voltages, multiple stages of charge pump cell 10 can be cascaded together with terminal 14 of the previous cell coupled to terminal 12 of the next cell. For example, the first cell increases VHIGH1=VLOW1+voltage level of the clock signal, i.e., VHIGH1=0+3. In the second cell, VLOW2=VHIGH1, and VHIGH2=VLOW2+voltage level of the clock signal, i.e., VHIGH2=3+3=+6 VDC. Additional cells can be added to the charge pump circuit to achieve practically any voltage necessary for the application, e.g., VHIGH of 10th cell=+30 VDC.
Charge pump cell 10 is subject to internal latch-up, particularly during initial cycles of the clock signal. Latch-up inhibits normal operation of the charge pump circuit. In some cases, the internal latch-up can be traced to an activation of various vertical and lateral parasitic pnpn or npnp structures in transistors 24 and 32.
FIG. 2 shows a cross sectional view of transistors 22 and 24 from FIG. 1. Substrate 40 includes p-type semiconductor material, e.g., base silicon substrate doped with boron or gallium. A deep n-well 42 is formed in surface 44 of substrate 40 by doping with n-type material, e.g., ion implantation of phosphorus or arsenic. P-region 46 is formed in n-well 42 as the drain of transistor 22 coupled to node 34. P-region 48 is formed in n-well 42 as the source of transistor 22 coupled to terminal 14. Gate structure 50 overlies the p-channel between p-region 46 and p-region 48 and is coupled to node 26. A vertical parasitic pnp is formed between p-region 46, n-well 42, and p-substrate 40. N-region 52 is formed in n-well 42 for good ohmic contact to terminal 14 and VHIGH in order for transistor 22 to sustain high voltages and exhibit low drain-source resistance in the conductive state (RDSON). In a similar manner, n-well 56 is formed in surface 44 of substrate 40 by doping with n-type material. N-region 58 is formed in n-well 56 for good ohmic contact to terminal 60 operating at VSS, e.g., ground potential. N-well 56 coupled to VSS represents other devices in the vicinity of charge pump cell 10. A lateral parasitic npn is formed between n-well 42, p-substrate 40, and n-well 56.
A deep n-well 64 is formed in surface 44 of substrate 40 by doping with n-type material, e.g., ion implantation of phosphorus or arsenic. N-well 64 is typically floating. A local p-well 66 is formed within n-well 64 by doping with p-type material, e.g., ion implantation of boron or gallium. N-region 68 is formed in p-well 66 as the drain of transistor 24 coupled to node 34. N-region 70 is formed in p-well 66 as the source of transistor 24 coupled to terminal 12 and VLOW. Gate structure 72 overlies the n-channel between n-region 68 and n-region 70 and is coupled to node 26. P-region 74 is formed in p-well 66 for good ohmic contact to terminal 12 and VLOW in order for transistor 24 to sustain high voltages and exhibit a low impedance RDSON. A lateral parasitic npn is formed between n-well 56, p-substrate 40, and n-well 64. A vertical parasitic npn 76 is formed between n-region 68, p-well 66, and n-well 64. A vertical parasitic pnp 78 is formed between p-well 66, n-well 64, and p-substrate 40.
One of the potential causes of internal latch-up is the combination of parasitic pnp and npn structures and floating regions within the device, e.g., parasitic npn 76, parasitic pnp 78, and floating n-well 64. At start-up, there are no high voltages within charge pump cell 10, although VLOW may be higher than VHIGH, and VHIGH is higher or equal to Vsubstrate, which is a factor that increases the occurrence of latch-up. Recall that n-well 42 is coupled to local VHIGH and p-well 66 is coupled to local VLOW with respect to charge pump cell 10 with n-well 64 floating. The initial low value of VHIGH creates a possibility for internal latch-up of the charge pump cell by forward biasing of one or more parasitic pnp and npn structures. Charge pump cell 10 receives voltages from CLK and nCLK through capacitors 20 and 28. CLK and nCLK cause charges to be injected into p-well 66, n-well 64, and substrate 40, which can forward bias and activate parasitic npn 76 and parasitic pnp 78, or other parasitic npn and pnp structures. The combination of two or more parasitic pnp or npn structures activated by accumulation of the injected charges latches the conductive state of the parasitic pnp and npn structures like 76-78 and shorts n-region 68 to n-well 64 or p-well 66 to substrate 40. Alternatively, latch-up can be triggered by the parasitic pnp or npn structures and resistivity of substrate 40. The injection of carriers from the clock signal coupling through capacitors 20 and 28, substrate bounce, or other spurious voltages activates two or more parasitic pnp or npn structures in a positive feedback loop to latch a parasitic pnpn or npnp combination. Once turned on, a large current flows through the parasitic pnpn and npnp in a self-maintained manner. The internal latch-up is particularly sensitive to high power supply voltages and high temperature. An internal latched condition for charge pump cell 10 inhibits normal operation and can increase power consumption. The power drain is problematic in portable battery applications and can potentially damage the circuit by excessive power dissipation.